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1. #Uefitool gigabyte how to
2. #Uefitool gigabyte update
3. #Uefitool gigabyte Patch
4. #Uefitool gigabyte software
5. #Uefitool gigabyte code

So, what has been actually done? 18h is a value to be programmed to the HOSTC register of the SMBus Host Controller by BIOS. Now you can close QView by pressing Esc key. “Edit ON” must be displayed when you hold Alt key and press down F3 key.

#Uefitool gigabyte code

OK, enable code editing by pressing Alt+F3. Your result should look like as shown below.Įverything you need is to change “push 00000018” to “push 00000008”. Activate 32-bit code addressing by pressing F2 key and move the cursor a few lines above by using up arrow key. Switch from the HEX mode to the Assembler mode by pressing F4 key. QView will find this string as shown below. Press F7 to call the search string dialog box and enter BF40B00F as HEX code to be searched. Press Alt+F to select and open the section file. Since it is a 16-bit application, please ignore any warning Windows messages. After running QView, press Alt+D to select the drive letter where the SMBus PE32 section file is saved. Now you can run QView utility to find something that matches our search criterion. After encoding the search criterion would be “F80BF040” or “F00BF040”.

#Uefitool gigabyte software

To access this location in the memory mapped space software encodes both the addresses using the specific formula: PCIEXBAR+(Bus number) +(Device number)+(Function number)+(Register number), where PCIEXBAR stands for PCI Express Register Range Base Address Register which may be set to F8000000h or F0000000h by default. According to the Intel 8 Series PCH datasheet SMBus Host Controller registers are located in the PCI configuration space at address “Bus:0, Device:1F, Function:3” and the HOSTC register has address 40h. But before patching we need any search criterion.

#Uefitool gigabyte Patch

The next step is to patch the SMBus PE32 section file. Right-click on the “PE32 image section” and select “Extract as is…” to save it to file.ĭo not close UEFITool since you will need it to perform the final step. Double click on the “Unicode text "SmBusPei" found in User interface section at offset 0h” string to open the found node in the modules tree. UEFITool should find a module that contains PE32 image with routines for SMBus Host Controller initialization. Activate the “Text” tab and enter “SmBusPei” without quotes to find this entrance. From the “File” main menu select “Search…” to call the Search dialog box. In this case you can use a simple utility of HxD.Īfter running UEFITool, go to the “File” main menu and select “Open image file…” to open your downloaded BIOS firmware file. Keep in mind that any attempt to lunch QView on 64-bit Windows fails. But this tool is good at disassembling which we need to examine BIOS code. You can use any other HEX editor if you are not familiar with QView. Also, we will use UEFITool 0.20.4 utility to edit BIOS sections and QView 2.90 file editor for viewing and patching extracted BIOS section files.

#Uefitool gigabyte update

OK, we have downloaded the latest BIOS update file for the ASUS H97-PRO Gamer motherboard for our experiment. So, our goal is to modify BIOS firmware the way it does not set bit 4 of the HOSTC register.

Unfortunately, our investigations confirmed that the bit is set by BIOS again once the hard reset has been initiated. The PCH asserts PLTRST# during power-up and when software initiates a hard reset sequence through the Reset Control register (I/O port CF9h). The PCH asserts this signal to reset devices on the platform (such as SIO, FWH, LAN, processor, and so on). This bit can be cleared by on PLTRST# assertion only. ASUS, MSI, Biostar and other motherboard manufacturers meet this requirement, although ASRock, for example, does not protect SPD from programming within BIOS firmware. According to the bit description it should be set to “1”. So, if we open the Intel 8 Series PCH datasheet (public edition) on page 667 we will find that the Host Configuration Register (HOSTC) of the SMBus Controller uses bit 4 called “SPD Write Disable” that was previously reserved. The only working solution is to modify BIOS. Unfortunately, software can’t temporarily bypass this restriction in Windows session. In some cases it was the only way to increase the memory bandwidth on notebooks. This means Intel does not want SPD to be programmed any more. The “SPD Write Disable” feature is implemented within Intel 9 Series Chipset Family PCH and X99 Chipset PCH as well. Now writes to SMBus addresses 50h - 57h are disabled by default via SMBus Host Controller registers. With release of 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH) Intel introduce a great surprise for all of us.

#Uefitool gigabyte how to